Routing is the process of moving a packet of information or data from source to destination, enabling messages to pass from the server to the client network. The address within the packet should be matched with the address within the output port. This paper introduces the development of a verification environment of a 1x1 router design using various System Verilog Constructs such as pack and unpack operations, Program block, interface, clocking blocks, and Oops concepts (class, methods) and has been extended to the verification environment of 4x4 router. Development of the Verification Environment is done using system Verilog coding and verified using EDA-playground (Mentor Questa). The functionality of the design is successfully tested and the routers are able to transmit minimum (2 bytes) to maximum (1990bytes) payload data to the destination address.